1. Field of the Invention
The present invention relates to an optical scanning apparatus for use in a laser printer, a laser facsimile receiver, etc..
2. Description of the Prior Art
Optical scanning apparatus are used for scanning a desired surface with a light beam to write information on the surface. In such optical scanning apparatus, the light beam is deflected at a constant angular velocity by means of a rotating light deflector such as a polygonal mirror or a hologram scanner. To make the scanning speed constant on the surface being scanned, an f.theta. lens is generally employed in the optical scanning apparatus. Since the f.theta. lens is expensive, however, there has been a demand for an optical scanning system which has no such f.theta. lens. There has recently been proposed a polygonal mirror which does not scan a light beam at a constant angular velocity (see Japanese Patent Application No. 59(1984)-274324). No f.theta. lens can be used with such a proposed polygonal mirror since any f.theta. lens would fail to make the scanning speed constant.
An image scanning clock signal is employed to turn on and off a scanning light beam when a desired surface is scanned therewith. The image scanning clock signal has a frequency fk expressed by 1/T where T is a time period assigned for writing information corresponding to one pixel. Where no f.theta. lens is employed, the speed at which a surface is scanned with a scanning light beam is not constant. Therefore, if the frequency fk of an image scanning clock signal were constant, the information written by the scanning light beam would be distorted.
FIG. 3 of the accompanying drawings illustrates an optical system in an optical scanning apparatus. A light beam L is deflected at a constant angular velocity by a rotating polygonal mirror 32, and converged by a condenser lens 34 onto the surface of a photoconductive photosensitive body 30. The light beam L is generally a laser beam emitted from a gas laser or a semiconductor laser. Distances l, h as defined in FIG. 3 are related as follows: EQU h=l.multidot.tan.theta.
Assuming that the angular velocity of the polygonal mirror is expressed by .omega..sub.0 (constant), since the angular velocity of the scanning light beam is given by d.theta./dt=2.omega..sub.0 =.omega. (constant), the scanning speed is expressed as follows; ##EQU1## If the length of a scanned area is 2H and H+h=h', then ##EQU2## Assuming that there are 2n.sub.o pixels within the scanning area length 2H, the scanning speed Vn at the nth pixel as counted from the lefthand scanning starting edge of the scanning area is given by: ##EQU3## where d is the width of one pixel. Inasmuch as the frequency fk of the image scanning clock signal is Vn/d, ##EQU4##
Therefore, by varying the image scanning clock frequency fk for each pixel according to the equation (1), the desired surface can be optically scanned without distorting written information even if no f.theta. lens is employed. The timing or period of varying the image scanning clock frequency is derived from a count value produced by starting to count the clock signal upon generation of a synchronizing signal from a light sensor 36 placed on the scanned surface or in a position equivalent to the scanned surface.
A generator for generating the image scanning clock signal comprises an oscillator, a first frequency divider, an up/down (U/D) counter, a control circuit, and a phase-locked loop (PLL) circuit. The oscillator generates a reference clock signal having a constant frequency F.sub.0. The first frequency divider frequency-divides the reference clock signal to produce a position control clock signal. The U/D counter changes the frequency-dividing ratio N of the first frequency divider (where N is a natural number ).
The control circuit operates as follows: The scanning area is divided into K blocks BLi (i=1 through K). The U/D counter is driven at every Mi pulses (i=1 through K) of the position control clock signal for the ith block BLi, so that the frequency-dividing ratio N is successively changed throughout the entire scanning area based on the prescribed finite sequence Mi (i=1 through K). More specifically, if the frequency-dividing ratio N has an initial value N.sub.0, then the frequency of the position control clock signal is initially f.sub.0 /N.sub.0. When Ml pulses of the position control clock signal are counted in the first block BL1, the control circuit enables the U/D counter to change the frequency-dividing ratio N.sub.0 of the first frequency divider to N.sub.1 (N.sub.0 +.DELTA.N), so that the frequency of the position control clock signal becomes f.sub.0 / N.sub.1. When Ml pulses of the clock signal having such a new frequency are counted, the frequency-dividing ratio N.sub.1 is changed to N.sub.2. The above cycle is repeated n 1 times. In the second block BL2, the cycle of changing the frequency-dividing ratio at every M2 pulses of the position control clock signal is repeated n2 times. Such a process is carried out for each of the blocks. Therefore, in the ith block BLi, the frequency-dividing ratio is changed ni times at every Mi pulses of the position control clock signal.
The PLL circuit is composed of a phase detector, a low-pass filter, a second frequency divider, and a voltage-controlled oscillator, the second frequency divider having a fixed frequency-dividing ratio M. The PLL circuit generates an image scanning clock signal having a frequency which is successively variable with the sequential change of the frequency of the position control clock signal.
The above image scanning clock generator will be described with reference to FIG. 1. The PLL circuit comprises a phase detector 18, a low-pass filter 20, a voltage-controlled oscillator 22, and a second frequency divider 24. A reference clock signal of a frequency f.sub.0 generated by an oscillator 10 is frequency-divided by a first frequency divider 12 into a position control clock signal having a frequency of f.sub.0 /N, which is applied to a control circuit 16 and the phase detector 18.
The phase detector 18 compares the phases of the position control clock signal and a clock signal CLA from the second frequency divider 24, and applies the phase difference as a pulse signal to the low-pass filter 20. When the phase difference information is delivered through the low-pass filter 20 to the voltage-controlled oscillator 22, the oscillator 22 produces a clock signal having a frequency commensurate with the output voltage of the low-pass filter 20. The clock signal generated by the oscillator 22 serves as an image scanning clock singal. The image scanning clock signal is then frequency-divided by the frequency divider 24, which applies the clock signal CLA to the phase detector 18 in which it is compared with the position control clock signal.
The frequency of the clock signal generated by the voltage-controlled oscillator 22 remains unchanged if there is no phase difference between the clock signal CLA and the position control clock signal which are compared in phase by the phase detector 18. This condition is referred to as an equilibrium condition of the PLL circuit. For example, if the frequency of the position control clock signal is f.sub.0 /N under the equilibrium condition, then the frequency of the clock signal CLA is also f.sub.0 /N. Therefore, the frequency fk of the clock signal produced by the voltage-controlled oscillator 22 is expressed by: EQU fk=f.sub.0 .multidot.(1/N).multidot.M=f.sub.0 .multidot.(M/N)
When the frequency-dividing ratio of the frequency divider is changed from N to N', the frequency of the position control clock signal becomes f.sub.0 .multidot.(1/N'), creating a phase difference between the position control clock signal and the clock signal CLA. Accordingly, the frequency fi of the clock signal produced by the voltage-controlled oscillator 22 is also changed successively at a constant rate from f.sub.0 .multidot.(M/N) to f.sub.0 .multidot.(M/N'). Therefore, by varying the frequency/dividing ratio N of the frequency divider 12, the frequency fk of the image scanning clock signal can be successively changed.
The control circuit 16 produces a clock signal CK for enabling a U/D counter 14 to produce preset varies for frequency-dividing ratios of the frequency divider 12, a signal EN for enabling the U/D counter 14 to count the clock signal CK, and a mode signal U/D for selecting an up-count or down-count mode.
The mode signal U/D is generated so that the U/D counter 14 changes from the up-count mode (or down-count mode) to the down-count mode (or up-count mode) in the vicinity of an extreme value of the scanning speed.
When the clock signal CK is applied to the U/D counter 14, it updates the preset value to change the frequency-dividing ratios of the frequency divider 12.
The clock signal CK is generated for each block BLi (i=1 through K) based on the finite sequence Mi (i=1 through K), as described above. Thus, Mi and ni are preset for each block. In the ith block BLi, the clock signal CK is generated from the control circuit 16 each time Mi pulses of the position control clock signal are supplied, and hence the clock signal CK is generated ni times in the block Bli.
The block number K and the values of Mi, ni are selected so that the frequency fk of the image scanning clock signal generated by the voltage-controlled oscillator 22 will vary according to the variation of the scanning speed, e.g., will well approximate the equation (1), for example. The block number K and the values of Mi, ni are determined experimentally or theoretically according to design conditions.
FIG. 4 shows, by way of example, an ideal pattern in which the image scanning clock frequency fk varies (curve 4-1) and a step-like pattern in which a clock frequency f'k varies by changing the frequency-dividing ratio. The numerals 5, 6, 10, 16 below the frequency-changing steps correspond to M1, M2, M3, M4 with the righthand end of the graph being a scanning starting end. It will be noted that n1=6, n2=9, n3=3, n4=5. The graph only shows a righthand half of a symmetric step-like pattern, and M5=10, n5=3, M6=6, n6=9, M7=5, n7=6. FIG. 4 indicates that the block BLi is a region in which the continuous curve of the frequency fk approximates a straight line, and the horizontal widths of the steps in each block are equal to each other. The clock frequency f'k corresponds to M times the position control clock frequency. Although the clock frequency f'k itself varies in a step-like manner, the frequency of the actual image scanning clock signal is continuously changed by the PLL circuit to well approximate the curve 4-1.
FIG. 2 is a timing chart explanatory of operation of the circuit shown in FIG. 1. Since the up-count and down-count modes of the U/D counter 14 are changed in the vicinity of an extreme value of the scanning speed, the frequency-dividing ratio N and the frequencies f.sub.0 /N, fk are symmetric with respect to a position in the vicinity of such an extreme value.
The synchronizing signal is generated from the light sensor 36 shown in FIG. 3 to initialize the first frequency divider 12. The synchronizing signal is also applied to the control circuit 16.
The signal EN energizes the counter upon elapse of a preset time Ta after the synchronizing signal has been received, and de-energizes the counter upon elapse of a preset time Tb after the desired area or printing zone has been scanned. At the same time the counter is de-energized, the frequency-dividing ration N is fixed to the initial value.
The optical scanning apparatus also has a circuit for generating a signal indicating a recording position. This circuit is initialized by the synchronizing signal from the light sensor 36 to count the position control clock signal from the frequency divider 12, and a generates a recording position signal when the count changes from one value to another value. The recording position signal and the image scanning clock signal are applied to an external device, which issues an image signal in synchronism with the image scanning clock signal when the recording position signal is applied. The image signal is applied to a modulator to modulate the light beam L, e.g., to turn on or off the semiconductor laser which generates the light beam L, for thereby forming a latent image on the photosenstive body 30.
With the optical scanning apparatus described above, however, the synchronizing signal from the light sensor 36 tends to fluctuate because of manufacturing or operating errors of the rotating polygonal mirror or light deflector 32, causing the position control clock singal from the frequency divider 12 and the clock CLS from the frequency divider 24 to go out of phase with each other. Therefore, the image scanning clock signal and the recording position signal are also caused to be brought out of phase with each other, with the result that the image signal may be partly erased, thus lowering the quality of the recorded image.
Furthermore, in the event that the rotating light deflector, the optical axis, or the light sensor suffers a positional error, the characteristic curve for the correction of the frequency of the image scanning clock signal and the characteristic curve for the changing of the scanning speed are deviated from each other for thereby impairing linearity and magnification error, and hence the image quality. The term "linearity" used herein indicates, for example, variations in the pitch between straight lines that are recorded by the scanning beam at equal intervals.